Thesis Defense: Soroush Araei

Tuesday, July 29
1:00 pm - 2:00 pm

Grier Room A (34-401A)

đź“… Date: Tuesday, July 29, 2025
đź•™ Time: 1:00 PM

📍 Location: Grier Room A (34-401A) / Zoom:  https://mit.zoom.us/j/93908105610

Title:  Reconfigurable and Interference-Tolerant Receivers for Next Generation Wireless Systems

Abstract:

An “all-in-one” radio, programmable across the sub-7 GHz spectrum, offers significant hardware efficiency for 5G systems. However, addressing strong interferers in this wide and congested spectrum remains a major design challenge. N-path filters offer a promising solution for efficiently suppressing interference, thanks to their clock-controlled reconfigurability and excellent linearity against in-band and adjacent-channel blockers. While widely adopted in modern receiver architectures, these switch-capacitor circuits remain inherently vulnerable to blockers at clock harmonics, due to their hard-switching nature. These blockers, common in 5G bands, pose a key bottleneck, delaying the realization of fully integrated multi-band, multi-mode radios.


This dissertation introduces fully passive topologies to address this challenge. The first design leverages simultaneous charge sharing and capacitor stacking to implement harmonic rejection filtering. It operates entirely without active circuitry and exhibits exceptionally low loss. A second-generation technique, termed “harmonic reset switching”, builds on this approach by rejecting harmonic blockers directly at the driving point of the N-path filter, achieving superior performance with reduced circuit complexity. As a result, existing reconfigurable receiver topologies can be seamlessly transformed into harmonic blocker–resilient architectures. For example, a taped-out mixer-first receiver adopting this technique achieves a 100x improvement in third-harmonic blocker tolerance compared to state-of-the-art broadband receivers. This dissertation also proposes a reconfigurable receiver for IoT-class radios, tolerant to both close-in and far-out blockers. A scalable clock bootstrapping technique is proposed to enhance linearity while maintaining both power and cost efficiency. All designs are validated through fabricated prototypes in advanced 22 nm and 45 nm silicon-on-insulator (SOI) technologies. By addressing this longstanding challenge, this work paves the way for fully reconfigurable, interference-resilient radios for 5G and beyond.

Thesis committee:

Prof. Negar Reiskarimian (Advisor)
Prof. Ruonan Han
Prof. Harry Lee

Details

  • Date: Tuesday, July 29
  • Time: 1:00 pm - 2:00 pm
  • Category:
  • Location: Grier Room A (34-401A)