Thesis Defense: Lab-to-Fab Monolithic 3D Integrated Carbon Nanotube Transistors: Scaling and Reliability

Thursday, February 15
3:00 pm - 4:30 pm

Grier A (34-401A)

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By: Andrew Yu

Supervisor: Max Schulaker

Details

  • Date: Thursday, February 15
  • Time: 3:00 pm - 4:30 pm
  • Category:
  • Location: Grier A (34-401A)
Additional Location Details:

Abstract:

Conventional scaling of silicon integrated electronics can no longer yield improvements that keep pace with increasingly data abundant computing demands. Moreover, for data intensive computing applications, a majority of system energy is consumed moving data between compute and memory – which are often physically separate and spatially far apart. This is termed the memory wall. A promising solution to this problem is monolithic 3D integration, in which layers of compute and memory are designed and integrated together vertically in the same monolithic 3D nanosystem, connected by ultra-dense, nanoscale interconnects. This provides significant projected system-level energy-delay benefits beyond conventional scaling. However, conventional silicon logic and memory technologies are incompatible with such 3D integration and cannot be used to realize such 3D nanosystems.

In my defense, I will discuss how I developed and established a foundry monolithic 3D technology using back-end-of-line (BEOL) carbon nanotube FET (CNFET) + Resistive RAM (RRAM) stack over silicon CMOS that achieves comparable memory performance (read power, write energy/latency, endurance, retention, multiple bits-per-cell capability) in the same footprint as a conventional RRAM stack using front-end-of-line (FEOL) silicon FET access transistors. This is accomplished through the following: (1) I develop the first CNFET process that is lift-off-free and can scale to advanced process technology nodes, (2) I lab-to-fab transfer and adapt this process from an academic prototype into a commercial CMOS foundry process on 200 mm wafers at a 90 nm technology node equivalent, and (3) I improve the scaling, variation, and reliability of lift-off-free BEOL CNFET to achieve iso-performance, iso-footprint, and iso-reliability BEOL memory metrics. This process is established within SkyWater Technology Foundry (90/130nm technology node on 200 mm Si wafers) and an apples-to-apples comparison is made directly versus FEOL Si FET + RRAM fabricated on the same wafers, from the same foundry, at the same node

Zoom: https://mit.zoom.us/j/98283810474

 

 

Such BEOL CNFET + RRAM technology unlocks a large architecture design space with significant system-level energy-delay product (EDP) benefits vs. FEOL Si + RRAM-only designs, e.g., >5ยด EDP benefits for new iso-footprint, iso-memory-capacity monolithic 3D architectures uniquely enabled by new monolithic 3D physical design. In summary, this thesis experimentally implements and demonstrates foundry monolithic 3D using beyond-silicon nano-technologies as a complementary integration path for dramatically improving system-level energy-efficiency and performance.

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