RISC-V is Inevitable: Krste Asanović

Monday, March 20
1:00 pm - 2:00 pm



  • Date: Monday, March 20
  • Time: 1:00 pm - 2:00 pm
  • Location: 32-G449
Additional Location Details:

RISC-V has grown from a university project into a global open standard
with a thriving ecosystem comprising hundreds of collaborating
organizations, including most of the major companies in computing.
This talk will describe how RISC-V is inevitable across all of
computing, displacing legacy proprietary instruction sets. RISC-V’s
technical advantages include a greater inherent efficiency than
competing architectures, a sophisticated vector processing extension,
and natural support for customized instruction set extensions. But
more important that its technical advantages, RISC-V provides a
superior open-standard business model that encourages both competition
and collaboration, and which ensures long-term stability to protect
software investments.

Krste Asanović is a Professor in the EECS Department at the University
of California, Berkeley. He received a PhD in Computer Science from UC
Berkeley in 1998 then joined the faculty at MIT, receiving tenure in
2005. He returned to join the faculty at Berkeley in 2007, where he
co-founded the Berkeley Parallel Computing Laboratory (“Par Lab”), and
led the ASPIRE Lab, and co-led the ADEPT Lab. His main research areas
are computer architecture, VLSI design, parallel programming and
operating system design. He is currently Co-Director of the new
Berkeley SLICE lab, which is improving specialized computing
ecosystems, and is also an Associate Director of the Berkeley Wireless
Research Center. He leads the free RISC-V ISA project at Berkeley, is
Chairman of RISC-V International, and is a Co-Founder and Chief Architect
at SiFive Inc. He is an ACM Fellow and an IEEE Fellow.


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