Doctoral Thesis: GaN Complementary Metal–Oxide–Semiconductor (CMOS) Technology on GaN-on-Si
To be conducted via zoom
GaN, a wide band gap semiconductor, has some remarkable attributes like spontaneous and piezoelectric polarization charge, high electron mobility, and high saturation velocity which are useful for electronics. These properties enable n-channel GaN based transistors to operate at a higher switching speed, and at a higher power density than its Si counterpart. Because of these performance benefits, n-channel GaN transistors are establishing their way into high-voltage power electronics and wireless communication markets to replace Si, SiC, GaAs and other semiconductors. To realize the full potential of GaN, the need for a complementary circuit technology cannot be overemphasized. A high performance GaN CMOS technology could potentially find applications in data centers, electric vehicles, space electronics, on-chip power converters, beyond 5G base stations, and a plethora of other applications where Si falls short in terms of performance and efficiency. However, a major roadblock to realize such technology is the lack of high-performance GaN p-channel transistors that can be monolithically integrated with GaN n-channel devices. This thesis for the first time demonstrates a GaN CMOS technology on a 6 inch GaN-on-Si wafer by fabricating a monolithically integrated p-channel GaN transistor with an E-mode GaN n-channel device. High temperature characteristics of fundamental logic building blocks like inverters were measured up to 300 °C, demonstrating the potential of such technology for harsh environment electronics and space applications. However, the performance of the demonstrated technology was bottlenecked by the current density of the p-channel device. This thesis also shows clear pathways to improve the current density of GaN p-channel transistors by demonstrating a self-aligned gate and a FinFET technology for the p-channel device. Our demonstrated devices exhibit record performance in terms of on-current density, on-off ratio, subthreshold swing and on-resistance.
To learn more about our demonstrated GaN CMOS Technology come to my thesis defense.
- Date: Friday, January 7
- Time: 3:00 pm
- Category: Thesis Defense
- Location: To be conducted via zoom
Additional Location Details:
Thesis Supervisor, Prof. Tomas Palacios
To attend this defense, please contact the doctoral candidate for the link: