EECS Professor Judy Hoyt, also principal investigator in the MIT Microsystems Technology Laboratories, MTL, and her group have shown that they can build transistor chips in which up to five high-performance nanowires are stacked on top of each other. This design would allow nanowire transistors to pass up to five times as much current without taking up any more area on the surface on the chip. In the real world of transistor chip manufacture, this is a crucial step toward establishing the viability of silicon-nanowire transistors.
As described in the January 6, 2010 MIT News Office article "Straining forward: Nanowires made of ‘strained silicon’ — silicon whose atoms have been pried slightly apart — show how to keep increases in computer power coming," Hoyt and EECS graduate students Pouya Hashemi and Leonardo Gomez have manufactured nanowires with a diameter of only eight nanometers, which they described in a 2009 paper in the Institute of Electrical and Electronics Engineers journal Electron Device Letters. By contrast, the smallest elements of today’s computer chips are 45 nanometers across.
Hoyt and her graduate student team have improved the performance of silicon-nanowire transistors by prying the atoms of the silicon slightly farther apart than they would be naturally allowing electrons to flow through the wires more freely. Such “strained silicon” has been a standard way to improve the performance of conventional transistors since 2003 and Hoyt was one of the early researchers in the field.
As reported by the MIT News Office: “Starting in the early 1990s, she’s really played a pioneering role in strained-silicon technology,” says Tahir Ghani, director of transistor technology and integration for Intel’s Technology and Manufacturing Group. “She did a lot of this pioneering work that for the first time demonstrated that you can have significant performance gains by implementing strain into silicon technology.” Hoyt and her group’s work on strained-silicon nanowires, Ghani says, “combines the two key elements of transistors” — performance and space efficiency — “both of which are very key to scaling in the future. And so from that standpoint, it makes it very relevant for industry.”