Doctoral Thesis: Towards Low-Power yet High-Performance Networks-on-Chip


Event Speaker: 

Sunghyun Park

Event Location: 

Haus Room, 36-462

Event Date/Time: 

Friday, August 29, 2014 - 10:00am


A network-on-chip (NoC), the de-facto communication backbone in manycore processors, consumes a significant portion of total chip power, competing against the computation cores for the limited power and thermal budget. On the other hand, overall system performance of manycore chips increasingly relies on on-chip latency and bandwidth as core counts scale. My thesis aims to design low-power yet high-performance NoCs through circuit and microarchitecture co-design contrary to the traditional approaches where NoCs sacrifice latency and/or bandwidth for low-power operation.

I will first present our 4x4 mesh NoC chip design that tries to simultaneously optimize energy, latency and throughput for all kinds of traffic (unicasts, multicasts and broadcasts). Its extensive experiment results make it possible to accurately analyze energy/latency/throughput benefits and timing/area overheads of our virtually bypassed, broadcast-optimized NoC router design.

The second half of my talk will focus on our 3D-IC chip prototype of a through-silicon via (TSV) interconnect that can support simultaneously bi-directional (SBD) signaling. While TSVs offer an appealing solution to manycore architectures that require huge off-die bandwidth, existing TSV technologies impose considerable power and area overheads (using spare TSVs) to improve reliability. The proposed SBD TSV circuit, which consists of a half-clocked pre-emphasis Tx and a switched dual-tree sense amplifier Rx, shows better energy efficiency and smaller area than unidirectional TSVs.

Thesis committee:
Li-Shiuan Peh (supervisor)
Anantha Chandrakasan (supervisor)
Srini Devadas