Doctoral Thesis: InGaAs MOSFETs for Logic Applications

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Event Speaker: 

Jianqiang (Jerome) Lin

Event Location: 

Grier B, 34-401B

Event Date/Time: 

Tuesday, March 3, 2015 - 9:00am

Abstract:
 
InGaAs is a promising candidate as an n-type channel material for future CMOS due to its superior electron transport properties. Great progress has taken place recently in demonstrating InGaAs MOSFETs for this goal. Among possible InGaAs MOSFET architectures, the recessed-gate design is an attractive option due to its scalability and simplicity. This presentation will describe in detail a novel self-aligned recessed-gate fabrication process for scaled InGaAs Quantum-Well MOSFETs (QW-MOSFETs). Our design emphasizes scalability, performance and manufacturability by making extensive use of dry etching and Si-compatible materials. The fabrication sequence yields precise control of all critical transistor dimensions. This work achieved InGaAs MOSFETs with the shortest gate length (Lg=20 nm), and MOSFET arrays with the smallest contact size (Lc=40 nm) and smallest pitch size (Lp=150 nm), at the time when they were made. Using a wafer bonding technique, InGaAs MOSFETs were also integrated onto a silicon substrate.
 
The fabricated transistors show the potential of InGaAs to yield devices with well-balanced electron transport, electrostatic integrity and parasitic resistance. A device design optimized for transport exhibits a transconductance of 3.1 mS/µm, a record value for III-V FETs of any kind. Our precise fabrication technology has also allowed us to carry out a detailed study of the impact of channel thickness scaling on device performance.
 
The scaled III-V device architecture achieved in this work has also enabled new device physics studies relevant for the application of InGaAs transistors for future logic. A particularly important one is OFF-state leakage. For the first time, this work has unambiguously identified band-to-band tunneling (BTBT) amplified by a parasitic bipolar effect as the cause of excess OFF-state leakage current in these transistors. This finding has important implications for future device design.
 
 
Thesis Committee:
Prof. Jesús del Alamo (Thesis advisor)
Prof. Dimitri Antoniadis (Thesis advisor)
Prof. Tomás Palacios