Over the past decade, increasing the number of cores on a single processor has successfully enabled continued improvements computer performance. Further scaling these designs to tens and hundreds of cores, however, still presents a number hard problems, such as scalability, power efficiency, effective programming models, etc.
A key component of manycore systems is the on-chip network, which faces increasing efficiency demands as the number of cores grows. In this talk, we present three techniques for improving the efficiency of on-chip interconnects. First, we discuss PROM (Path-based, Randomized, Oblivious, and Minimal routing) and BAN (Bandwidth Adaptive Networks), techniques which offer efficient intercore communication for bandwith-constrained oblivious networks. Next, we present ENC (Exclusive Native Context), the first deadlock-free, fine-grained thread migration protocol developed for on-chip networks. ENC demonstrates that a simple and elegant technique in the on-chip network interconnect can provide critical functional support for higher-level application and system layers. Finally, we provide a realistic context by sharing our hands-on experience in the physical implementation of the on-chip network for EM2, an ENC-based 110-core processor in the 45nm ASIC technology.
Thesis Supervisor: Professor Devadas
For more information please contact: Myong Hyon Cho, mailto://email@example.com