CMOS scaling challenges in the increasingly power-constrained space requires innovation in materials, architecture, and process-design co-optimization. This talk will give a high-level overview on CMOS foundry technology architectures and how they may address both leakage and active power constraints while maintaining circuit performance. The presentation will also touch on 3D-IC concepts that are becoming mainstream as a means to address energy efficiency at system-level integration.
Dr. Meikei Ieong is currently a Sloan Fellows at MIT's Sloan School of Management. He is also a director at the Advanced Device Technology Division of TSMC and was the program director of its 28nm high-performance and mobile CMOS technologies. Prior to that, Dr. Ieong was senior manager at IBM’s T.J. Watson Research Center; he had the responsibility of creating and assessing nano-scale device technologies. His current research interests include nano-device technologies with emphasis on ultra low power and energy efficiency for computing, mobile, and bio applications.
Dr. Ieong is a senior member of the IEEE and has been an editor for the Transaction on Electronic Devices Since 2010. He was on the IEDM committee from 2002 to 2010 and was the Technical Program Chair in 2009 and General Chair in 2010. He also served on program committee in several international conferences. He has published more than 100 papers in referred journals and conference proceedings and more than 80 patents issued or pending.