Srini Devadas and Jacob White have been selected for their significant contributions to the Design Automation Conference (DAC), which celebrated its 50th anniversary June 2 - 6. Both were recognized for their impact on the course of DAC’s history.
Srini Devadas, the Edwin Sibley Webster Professor of Electrical Engineering and Computer Science at MIT and principal investigator in the Computer Science and Artificial Intelligence Laboratory (CSAIL) was recognized as DAC Top 10 Cited Author “for being among the top ten most cited DAC authors in DAC’s 50 year history." Devadas was also awarded the Best-Paper Hat Trick Award “for winning the DAC best paper award three times – the most in DAC’s 50 year history." Among his most cited works is “Physical unclonable functions for device authentication and secret key generation,” published in the Proceedings of the 44th annual DAC in 2007. This work, which led to development of a low-cost mechanism for authentication of silicon chips, formed the basis for the company Verayo, founded in 2005.
Professor Devadas has been a faculty member of the MIT Department of Electrical Engineering and Computer Science since earning his PhD from University of California at Berkeley in 1988. His broad range of research interests and projects include computer architecture, computer security, VLSI design, computer-aided design, hardware validation, network router hardware, computer security and computational biology. Prof. Devadas developed Aegis, a secure hardware processor that uses PUFs to generate secret keys from chip fabrication variations. As part of the Quanta Project Qumulus at MIT, Devadas and his research group have worked on trusted virtual computation and secure virtual storage. His group recently designed and implemented the Execution Migration Machine, a 110-core shared memory processor that uses fast hardware-level thread migration to significantly reduce on-chip network traffic. He is also a contributing member of bigdata@CSAIL.
The 50th DAC also recognized Srini Devadas for winning the DAC best paper award three times, the most in DAC’s 50 year history and the DAC 30 Club for publishing 30 or the most papers at DAC. Over the years, Devadas has pioneered work in a number of areas related to CAD, security and computer architecture. His early award-winning work involved developing a symbolic simulation method for analyzing the average and worst-case power estimation of combinational and sequential logic; this was among the first efficient and accurate power estimation methods developed. He has also served the MIT EECS Department as Associate Department Head (for Computer Science from 2005 to 2011) and as EECS Interim Department Head in the spring of 2011.
Jacob White, the Cecil H. Green Professor of Electrical Engineering and Computer Science and principal investigator in the Research Laboratory of Electronics at MIT, was honored at the 50th DAC with the ACM/IEEE A. Richard Newton Technical Impact Award in Electronic Design Automation for “seminal work on fast integral equation solvers for integrated circuit parasitic extraction.” White and Keith Nabors, who is currently a design engineer at Apache Design Systems, Ansys Inc., coauthored “FastCap: a multipole accelerated 3-D capacitance extraction program.” The work was published in the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, November 1991. Prof. White was also recognized at the 50th DAC for being one of the top 10 most prolific authors for DAC’s fourth decade.
Prof. White has served the EECS Department as Co-Education Officer since 2011. In 2011, he received an EECS department Jamieson Award for his contributions to course and curriculum development, having helped develop two graduate numerical courses as well as both of the department's new introductory courses, 6.01 and 6.02.
One of the most highly-cited DAC papers for both Professors Devadas and White was one they coauthored. The paper, “Estimation of average switching activity in combinational and sequential circuits” appeared in the Proceedings of the 29th ACM/IEEE Design Automation Conference in 1992. This widely-cited work, also co-authored by Abhijit Ghosh and Kurt Keutzer, addressed the problem of estimating the average power dissipated in VLSI combinational and sequential circuits, under random input sequences.