Advances in video compression, which have enabled us to squeeze more pixels through bandwidth-constrained channels, have been critical in the rapid growth of video. As we continue to push for higher coding efficiency, higher resolutions and more sophisticated multimedia applications, the required number of computations per pixel and pixel processing rate will grow exponentially. This poses significant power and performance challenges for battery operated devices such as smart phones and tablets, as well as emerging devices such as wearable cameras/displays and video sensors. In this talk, we’ll describe how joint algorithm and architecture design can be used to develop video algorithms that address these implementation challenges by exposing parallelism and reducing memory requirements, while still delivering high coding efficiency. We will also describe how this work was leveraged in the development of the recently ratified video coding standard High Efficiency Video Coding (HEVC).
Vivienne Sze received the B.A.Sc. (Hons) degree in electrical engineering from the University of Toronto, Toronto, ON, Canada, in 2004, and the S.M. and Ph.D. degree in electrical engineering from the Massachusetts Institute of Technology (MIT), Cambridge, MA, in 2006 and 2010 respectively. She received the Jin-Au Kong Outstanding Doctoral Thesis Prize, awarded for the best PhD thesis in electrical engineering at MIT in 2011.
Since September 2010, she has been a Member of Technical Staff in the Systems and Applications R&D Center at Texas Instruments (TI), Dallas, TX, where she designs low-power algorithms and architectures for video coding. She also represents TI at the international JCT-VC standardization body developing HEVC, the next generation video coding standard. Within the committee, she is the primary coordinator of the core experiment on coefficient scanning and coding.
She was a recipient of the 2007 DAC/ISSCC Student Design Contest Award and a co-recipient of the 2008 A-SSCC Outstanding Design Award. She received the Natural Sciences and Engineering Research Council of Canada (NSERC) Julie Payette fellowship in 2004, the NSERC Postgraduate Scholarships in 2005 and 2007, and the Texas Instruments Graduate Woman's Fellowship for Leadership in Microelectronics in 2008. In 2012, she was selected by IEEE-USA as one of the “New Faces of Engineering”.