Thesis Title: Precision Hybrid Pipelined ADC


Event Speaker: 

Mariana Markova

Event Location: 

38-466 (Jackson Room)

Event Date/Time: 

Tuesday, January 28, 2014 - 9:00am

Thesis committee :
Hae-Seung Lee (thesis supervisor)
David Perreault
Brian Brandt


Technology scaling poses challenges in designing analog circuits because of the
decrease in intrinsic gain and reduced swing. An alternative to using high-gain
amplifiers in the implementation of switched-capacitor circuits has been
proposed [1] that replaces the amplifier with a current source and a
comparator. The technique has been generalized to zero-crossing based circuits
(ZCBC). It has been demonstrated but not limited to single-ended and
differential pipelined ADCs, with effective number of bits (ENOB) ranging from
8 bits to 11 bits at sampling rates from 10MS/s to 100MS/s [1],[2],[3],[4],[5].

The purpose of this project is to explore the use of the ZCBC technique for
high-precision ADCs. The goal of the project is a 13-bit pipelined ADC
operating at up to 100MS/s. A two-phase hybrid ZCBC operation is used to
improve the power-linearity tradeoff of the A/D conversion. The first phase
approximates the final output value, while the second phase allows the output
to settle to its accurate value. Since the output is allowed to settle in the
second phase, the currents through capacitors decay, permitting higher accuracy
and power-supply rejection compared with standard ZCBCs. Linearization
techniques for the ramp waveforms are implemented. Linear ramp waveforms
require less correction in the second phase for given linearity, thus allowing
faster operation. Techniques for improving linearity beyond using a cascoded
current source are explored; these techniques include output pre-sampling and
bidirectional output operation. Current steering is used to minimize the delay
contributing to the first phase error and a high-speed rail-to-rail output
zero-crossing detector is implemented. In addition, overshoot reduction
calibration improves the linearity requirements of the final phase. Automated
background overshoot reduction is introduced though not included on the test

A test chip in 1V, 65nm CMOS process was designed to demonstrate the techniques
introduced in this work. The prototype ADC did not meet the intended design
goal and achieved 11-bit ENOB at 21MS/s and SFDR of 81dB. The main performance
limitations are lack of overshoot reduction in the third pipeline stage in the
prototype ADC and mid-range errors, introduced by the bidirectional ramp
linearization technique, limiting the attainable linearity.
Sponsorship: CICS