Thesis committee :
Anantha Chandrakasan (supervisor)
Hae-Seung Lee (supervisor)
Analog-to-digital converters (ADCs) are essential building blocks in
many electronic systems which requires digital signal processing and
storage of analog signals. Traditionally, ADCs are considered a power
hungry circuit. This thesis investigates ADC design techniques to
achieve high-performance with low power consumption.
Two designs are demonstrated. The first design is a voltage scalable
zero-crossing based pipelined ADC. The zero-crossing based circuit
technique is modified and optimized to improve the limited ADC
resolution in nano-scaled CMOS technology. The proposed unidirectional
charge transfer scheme allows faster and more energy efficient operation
by eliminating unnecessary charging and discharging of the capacitors.
Furthermore, the reduced transient disturbance at the beginning of the
fine charge transfer phase improves the accuracy of the operation. Power
supply scaling enhances power efficiency at low sampling rates much like
in digital circuits and widens the conversion frequency range where the
ADC operates with highest efficiency.
The second design is a high speed time-interleaved (TI) SAR ADC with
background timing-skew calibration. A time-interleaved structure is
employed to improve the effective sampling rate without sacrificing
energy efficiency. SAR ADCs are used for each channel to make good use
of device scaling. The proposed ADC architecture incorporate a flash ADC
operating at the full sampling rate of the TI ADC. The flash ADC output
is multiplexed to resolve MSBs of the SAR channels. Because the
full-speed flash ADC does not suffer from timing-skew errors, the flash
ADC output is also used as the timing reference to estimate the
timing-skew of the SAR ADCs.