Guide to Graduate Study in Area V: Materials and Devices
Microsystems
MIT is engaged in a comprehensive program of research into various aspects of microelectronics that encompasses fabrication, design, and architecture. The research in Area V relevant to microelectronics includes work on: semiconductor materials and material processing; the development of the technology for producing structures of nanometer dimensions; the development of novel devices and device structures, and microelectrical-mechanical (MEMS) devices.
The physical resources to support Microsystems Research are contained in the Microsystems Technology Laboratories (MTL), which occupies Bldg. 39 and parts of Bldg. 38. This complex provides office space for approximately 60 graduate students, CAD, testing and masking facilities, and contains the following major laboratories: (For a more complete description see the MTL Web page.)
> Integrated Circuits Research Laboratories (ICL):
This is a complete state-of-the-art integrated circuits and fabrication laboratory, containing 2800 sq. ft. of class 10 space, and equipped with a full complement of facilities for the fabrication of microelectronic circuits with features at or below the 1 µm level. The ICL, as well as the Technology Research Laboratory, is staffed and operated by professional personnel, and qualified students can make arrangements for direct access.
> Technology Research Laboratory (TRL):
This laboratory provides nearly 4,000 sq. ft. of space, with 2,200 sq. ft. being class 100 space, where graduate students and staff carry out novel process development. A wide variety of common-use and research-group specific equipment is housed in the TRL.
> NanoStructures Laboratory:
Research in this laboratory is directed toward developing the advanced process techniques needed for fabricating surface structures with feature sizes ranging from nanometers to micrometers. Facilities are available for photo-, interferometric, electron-beam, and x-ray lithography. In addition, the NSL houses materials and processing facilities for etching (chemical, plasma and reactive-ion), lift-off, electroplating, sputter deposition and e-beam evaporation. See: http://nanoweb.mit.edu/.
> Nanoprecision Deposition Laboratory:
Within the Research Laboratory of Electronics, the Nanoprecision Deposition Laboratory is a state-of-the-art facility established for the layer-by-layer deposition of materials, especially compound semiconductors and dielectrics. Two deposition techniques are available including molecular beam epitaxy, for III-V compound semiconductors containing arsenic, phosphorus, and antimony, and ion beam deposition for dielectrics of silicon dioxide or tantalum pentoxide. In the photo, the molecular beam epitaxy system has two ultrahigh vacuum reactors that are interconnected to a central cluster tool for wafer loading and processing. The molecular beam epitaxy system is capable of handling more than one substrate or wafer and is also available to deposit onto wafers having up to 8 inch diameters. See: http://web.mit.edu/cbegroup/www/Laboratory.html.
> Scanning-Electron-Beam Lithography Facility (SEBL):
The scanning-electron-beam lithography facility enables the writing of patterns of arbitrary geometries with minimum features as fine as 17 nm. The facility includes two SEBL systems, a VS26 and a Raith 150. The former was developed at IBM Research Center specifically for electron-beam lithography and operates at 50 keV. The Raith 150 is an SEM modified for electron-beam lithography and has a maximum operating voltage of 30 keV. See: http://www.rle.mit.edu/sebl/.