MIT Department of Electrical Engineering & Computer Science

The Limit of CMOS Scaling: How Far Can We Extend It?

Yuan Taur
IBM Research

Tuesday, April 11, 2000
4:00 PM (reception 3:30)
Edgerton Hall, Room 34-101
MTL VLSI Seminar

Abstract

Beginning with a review of MOSFET scale length theory, this talk focuses on the limit of CMOS scaling and discusses how far it can be extended. Nonscalability of silicon bandgap and thermal voltage kT/q forces the electric field in a scaled MOSFET to rise. When the smallest dimensions in the device approach atomic scales, quantum mechanical tunneling takes place from gate to channel, drain to body, and source to drain, ultimately causing loss of control of the standy leakage. Several proposals to extend the limit of CMOS scaling, e.g., super-halo, high-k gate dielectrics, thin SOI, double-gate MOSFET, and low temperature CMOS, will be examined in depth.