MIT Department of Electrical Engineering & Computer Science

Managing the Interconnect Continuum...from Si to Package to Board

Bill Siu
Intel Corporation

Tuesday, March 28, 2000
4:00 PM (reception 3:30)
Edgerton Hall, Room 34-101
MTL VLSI Seminar

Abstract

Advances in VLSI technology, microprocessor architecture, and circuit design techniques now enable logic chips and microprocessors to operate in excess of 1GHz. As we reach these speeds, the characteristics and performance of interconnects play an ever-increasing role. Significant research has been spent on VLSI interconnects with the much touted transition to copper metallurgy and low K dielectrics as the next major advance. However, to solve these problems in an optimal way, it is not just the interconnects on the chip but the entire Interconnect Continuum from the chip, through the package and the system board. In this talk, we present a holistic view of the challenges and potential directions for this Interconnect Continuum. It is seen that performance can be affected by architecture and partitioning of the chips and the systems. Furthermore, by careful considerations of these factors, high speed opearations can be accomplished in an elegant and economical way. The advent of new interconnect technologies such as copper metalization, flip-chip and organic substrates play key roles in managing and optimizing the outcome.