MIT Department of Electrical Engineering & Computer Science

Efficient portability across memory hierarchies

Enoch Peserico

Friday, October 29, 1999
1:00 PM
NE43-516
TDS Seminar

Abstract

In recent years the gap between processor and memory speed has been steadily increasing. This problem, in turn, has led to a deeper and deeper hierarchical structure of memory: even the lowliest PC on the market today has registers, L1 cache, L2 cache, L3 cache, main memory, virtual memory on disk, and perhaps access to a LAN and to the Internet.

In this contest it becomes important to study how code behaves as the parameters of the hierarchy (e.g. cache size, main memory size etc.) change. In particular it is interesting to study to what extent code can be made efficiently portable, i.e. to what extent we can write "once and for all" code which behaves on any memory hierarchy (almost) as efficiently as code written for and tailored to that specific hierarchy.