TR 11-12:30, 34-304
3-0-9
Prerequisite: 6.152J or equivalent
Prof. Rafael Reif, 39-321, x7317
Many advanced integrated circuits today use multilevel interconnection schemes. Moreover, advanced logic circuits such as microprocessors are now facing density and performance limits dictated in large measure by interconnect performance. It is ithe purpose of this course to provide a fundamental and practical understanding of the major process technologies used in the fabrication of multilevel interconnects. Specific topics include thin film deposition technologies for dielectric and conducting layers (e.g., sputtering, chemical vapor deposition -CVD- and plasma-enhanced chemical vapor deposition), plasma etching, planarization technologies, via filling, contact technologies, and manufacturing yield and reliability. The deposition and etching of typical materials employed in present and potentially future multilevel technologies (e.g., titanium, titanium nitride, tungsten, CVD aluminum, TEOS oxides, low-K dielectric constant films, etc.) will be discussed.
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Created: Jun 24, 1996
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Modified: Jun 24, 1996|
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