MIT Department of Electrical Engineering & Computer Science
EECS Fall 1996 Catalogue Supplement
6.915 Digital Systems Engineering
TR 11-12:30, 36-144
3-0-9
Prof. William Dally, NE43-620, x6043
This subject is intended to fill a gap between circuit design (6.002) and logic design or architecture (6.004/6.823). It can be taken by any undergraduate who has completed 6.002. Topics include:
1. What is digital systems engineering?
2. Wires: properties and modeling
3. Circuits: review and basic circuit building blocks
4. Noise in digital systems
- sources of noise
- noise management techniques
- noise immunity and noise margins
5. Power distribution
- the distribution problem
- on-chip distribution
- global distribution
- shunt and series regulators
- bypass capacitors
- examples
6. Signalling conventions
- choice of symbols: binary vs. multi-level
- current vs. voltage mode signalling
- references and noise rejection
- bidirectional signalling
- band-limited signalling
- examples
7. Timing conventions
- timing basics
- timing noise: skew and jitter
- signals and events
- event encoding
- synchronous timing
- pipelined timing
- closed-loop timing systems
- clock distribution and deskew
8. Synchronization
- the synchronization problem
- synchronization failure and metastability
- the synchronization hierarchy
- mesochronous synchronizers
- periodic synchronizers
- asynchronous design
9. Signalling circuits
10. Timing circuits
11. Case studies
URL of this page:
http://www-eecs.mit.edu/AY96-97/fall-cat/6915.html
Editor: Mibsy Brooks
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Created: Jun 12, 1996
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Modified: Jun 12, 1996
Related page: EECS Fall 1996 Catalogue Supplement
To MIT EECS home page
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and inquiries are welcome.