MIT Department of Electrical Engineering & Computer Science

MIT TOC SEMINAR

Overview of the RACE architecture for embedded multicomputing

Barry Isenstein

Mercury Computer Systems, Inc.

DATE: Wednesday, APRIL 12, 1995

TIME: Refreshments at 2:00pm
TALK AT 2:15pm

PLACE: NE43-518

This presentation provides an overview of the hardware architecture and the programming paradigm for the RACE=AE Series of realtime multicomputers from Mercury Computer Systems. As a reference point, we will compare the RACE approach with the more traditional supercomputers and massively parallel processor (MPP) machines. While the RACE Series delivers supercomputer-class performance, RACE products are not supercomputers and therefore are different.

At the heart of the difference between MPP and RACE multicomputers are the distinct problems they each address. Understanding this difference provides insight to programming and future directions for Mercury software. The different application spaces also dictate other fundamental differences between MPP and RACE products besides the programming paradigm. These include footprint, interconnect, external interfacing, memory design, and processor strategies. General application requirements will be discussed for a more complete understanding of solving problems in realtime multicomputing.

HOST: Professor Charles E. Leiserson