MIT Department of Electrical Engineering & Computer Science

April 4, 1995
3:30 Reception, 4:00 Lecture
Room 34-101, 50 Vassar Street

Title: Design Considerations and Tradeoffs for High Performance 0.25 um CMOS Technology

Mark Rodder
Texas Instruments
Dallas, Texas

I will discuss design issues and tradeoffs for 0.25 um CMOS technology. Choice of gate oxide thickness and supply voltage is determined from performance and reliability constraints including time-dependent-dielectric breakdown, hot-carrier lifetime, and gate-induced-drain leakage. Design/process dependence of performance and reliability (further including ESD related thermal breakdown) is investigated for variation of (a) channel doping (conventional and super-steep retrograde profile), (b) source/drain doping (including effect of pocket (halo) implant) and (c) source/drain anneal process. A figure-of-merit analysis is presented as a means of benchmarking technology compared to industry trend.