MIT Department of Electrical Engineering & Computer Science

March 21, 1995
3:30 Reception, 4:00 Lecture
Room 34-101, 50 Vassar Street

Title: Electrostatic Discharge (ESD) Protection for Advanced DRAMs, Microprocessors and Logic Chips in Shallow Trench Isolation and LOCOS CMOS Technologies

Steven H. Voldman
IBM Microelectronics Division
Essex Junction, Vermont

Electrostatic discharge (ESD) protection for advanced CMOS technologies becomes more difficult as MOSFET transistors continue to scale to sub-0.25 um dimensions. ESD networks must also address multiple power supply voltages, power-up sequence issues and increase in customer expectations of higher ESD robustness with each technology generation. The presentation will address an overview of ESD protection networks, semiconductor process sensitivities, ESD electrothermal simulation, novel ESD circuits, ESD scaling theory, design optimization and analytical models. Recent results will be shown in 16-Mb DRAMs, logic chips and RISC-based PowerPC architecture microprocessors in 0.5 and 0.25 um CMOS technologies.