MIT Department of Electrical Engineering & Computer Science

February 28, 1995
3:30 Reception, 4:00 Lecture
Room 34-101, 50 Vassar Street

Title: Low Voltage, Low Power DRAM Design Techniques

Howard Kalter
IBM
Burlington, Vermont

Low voltage circuit techniques for high density DRAMs, and the utilization of these techniques on a 16 Mb DRAM operating over the 2.5 V specification are presented. The design utilizes a P-array designed using a full VDD bit line precharge for fast signal development, optimal sense latch sensitivity, and low power. Performance and power are further enhanced by using a Digital Secondary Sense Amplifier (DSSA). Worse case module accesses of 55 nsec is obtained from chips built in a 0.5 um CMOS technology.