MIT Department of Electrical Engineering & Computer Science

Tuesday, February 7, 1995
3:30 Reception, 4:00 Lecture
Room 34-101, 50 Vassar Street

Title: Is a 0.35 um, 3.3V CMOS the Last Mainstream Bulk Generation?

Ghavam Shahidi
IBM
East Fishkill, New York

As the CMOS channel length been scaling into the sub-0.5 um range, the supply voltage has been dropping, but still kept at maximum value as allowed by reliability. The power consumption of the most advanced logic chips today is moving into 10's of Watts, and this has necessitated a look into faster drop of supply voltage for future bulk generations. Bulk CMOS performance is severely affected by drop in supply voltage.

In this talk it will be shown that CMOS on Silicon on Insulator (SOI) offers key advantages over bulk CMOS at low voltages. Work at IBM toward developing a low power CMOS on SOI, perceived problems with SOI, and steps underway to address such issues will be described.