MIT Department of Electrical Engineering & Computer Science

Massachusetts Institute of Technology

MTL VLSI SEMINAR

Tuesday
October 18, 1994
3:30 Reception
4:00 Lecture
Room 34-101
50 Vassar Street

Characteristics of CMOS Device Isolation for the ULSI Age

Andres Bryant
IBM Microelectronics Division
Essex Junction, Vermont

By 1980 LOCOS had become the standard MOSFET isolation technology. However, at the same time, the scalability of LOCOS for half-micron and sub-half-micron CMOS technologies was already being questioned. The issues were the lateral extent of the LOCOS bird's beak, non-planarity, thinning, and generation of stress induced silicon defects. Over the following decade, two different approaches to solve these problems were followed. One was the evolutionary development increasingly complex LOCOS processes and the other was the development of the radically different shallow trench isolation. Today, as we prepare for the 0.25 um 256 Mb DRAM generation and the ULSI era of the 21st century, the need for ideally scalable CMOS isolation technology becomes critical. The geometrical characteristics of ideally scalable isolation are planarity, independence of isolation width and depth, and an abrupt transition from active MOSFET regions to isolation regions. The purpose of this paper is to compare LOCOS based and trench based isolation technologies against these three characteristics, to discuss the electrical consequences of achieving the ideally scalable geometry, and to identify key process features that allow practical isolation technologies to approach this goal.