MIT Department of Electrical Engineering & Computer Science

MIT EECS
1994 (Fall Semester)
Colloquium Series

Monday, December 12, 1994

SOFTWARE COMPILATION OF HARDWARE SYSTEMS:
THE VIRTUAL WIRES APPROACH

Anant Agarwal
Department of Electrical Engineering and Computer Science
Massachusetts Institute of Technology

Field-programmable gate arrays (FPGAs) are a fast-growing technology that enables the implementation of reconfigurable logic systems. A mosaic of a few hundred FPGAs offers the potential to implement logic systems with millions of gates. Such reconfigurable logic systems offer the potential to construct customized hardware platforms for many applications that can outperform convential computers by several orders of magnitude.

A key to harnessing the power of reconfigurable systems is a compilation system that can automatically map a user's design into a multi-FPGA fabric. This talk will describe such a compiler system based on the technique of Virtual Wires. The talk will also use examples from logic simulation to demonstrate the cost and speed advantages of the Virtual Wires approach.

4-5 PM
Grier Room (34-401)
Refreshments 3:30