MIT Department of Electrical Engineering & Computer Science

MIT EECS
1994 (Fall Semester)
Colloquium Series

Monday, October 24, 1994

LOW POWER DESIGN TECHNIQUES FOR PORTABLE WIRELESS SYTEMS

Anantha Chandrakasan
M.I.T.
Department of Electrical Engineering
and Computer Science

Portable operation is becoming increasinly important for many of the most exciting new electronic products. The strict limitation on power dissipation which this imposes must be met by the designer while still meeting ever higher computational requirements. This is resulting in a need for a "Cold Chip" design strategy. To meet this need, a comprehensive strategy is required at all levels of the system design, ranging from algorithms and architectures used to the logic styles and the underlying technology. Potentially one of the most important techniques involves combining architecture optimization with voltage scaling, which allows a trade-off between silicon area and low-power operation. Several techniques can also be used to minimize the switched capacitance which includes optimizing signal correlations, choice of data representation, minimizing spurious transitions, optimizing sequencing of operations, activity driven power down, etc. Various support circuitry for low-voltage operation including level-converters and DC/DC converters will also be presented in the talk.

The various low-power techniques developed have been applied to the design of a low-power portable multimedia terminal that supports pen input, speech I/O, text/graphics and one way full-motion video. A set of six custom chips with protocol conversion, synchronization, error correction, packetization, buffering, video decompression and D/A converion combined consumes less than 5mW, which is three orders of magnitude lower than any existing solution

October 24, 1994
4-5pm
Grier Room (34-401)
Refrehment at 3:30 pm