MIT EECS
1994 (Fall Semester)
Colloquium Series
Monday, November 14, 1994
THE MESHSP: A PARALLEL DIGITAL SIGNAL PROCESSOR
Ira Gilbert
Lincoln Laboratory
Massachusetts Institute of Technology
The MeshSP architecture provides a simple and scalable solution for computationally demanding problems such as multi-dimensional signal processing. It comprises a mesh-connected array of identical slave processors under the control of a single master. Each slave consists solely of one Analog Devices SHARC chip (120 MFLOPS and 512 KBytes of on-chip memory). This hardware simplicity permits inexpensive construction of large MeshSP systems.
The first MeshSP system comprises an array of 64 processing elements,
yielding a peak throughput of 7.7 GFLOPS. It consists of two boards
in a personal computer. The system will be demonstrated near the end
of 1994, and be commercially available early in 1995.
4-5 PM
Grier Room (34-401)
Refreshments 3:30
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