MIT Department of Electrical Engineering & Computer Science

MIT EECS

1994 (Fall Semester)

Colloquium Series

Monday, October 17, 1994

SYNTHESIS FOR TESTABILITY

Srinivas Devadas
Massachusetts Institute of Technology
Department of Electrical Engineering and Computer Science

Logic testing is a very difficult problem and has traditionally been a post-design step; however, the impact of the design or synthesis process on the testability of the circuit is very profound. Recently, there has been an explosion of interest in incorporating testability measures in logic synthesis techniques. I will describe several approaches to the problem of synthesizing testable combinational and sequential logic.

One class of approaches constrains the synthesis procedure in order to restrict the final design to the space of fully testable solutions. The constraints on the synthesis procedure can result in area overheads. Another class of approaches relies on the paradigm that redundancy in a circuit, which renders a circuit untestable, is the result of a sub-optimal logic synthesis step. Thus, optimal logic synthesis can ensure fully testable combinational or sequential logic designs with minimal area.

4-5 PM
Grier Room (34-401)
Refreshments 3:30