MIT Department of Electrical Engineering & Computer Science

MIT EECS

1994 (Fall Semester)

Colloquium Series

Monday, October 3, 1994

FAST, LOW-POWER CHARGE-DOMAIN SIGNAL PROCESSING

A. M. Chiang
Lincoln Laboratory
Massachusetts Institute of Technology

In this talk, a charge-domain processing technique that combines the speed, power, and weight advantages of CCD computing units with the versatility and adaptability offered by digital CMOS control and memory units will be described. Such integration allows processors to perform faster, more complicated and flexible functions with smaller size, lower power than presently possible. As an example, a single-chip CCD/CMOS adaptive filter architecture implementing both an FIR filter and an LMS adaptive algorithm will be presented. The adaptive filter can be used as a NTSC/HDTV echo cancellor. The design and the performance of a 512-stage CCD/CMOS FIR filter will also be presented.

This work was sponsored by ARPA and the Department of the Air Force.

4-5 PM
Grier Room (34-401)
Refreshments 3:30