MIT Electrical Engineering and Computer Science EECS Event

Low Power Circuits and Technology for Wireless Digital Systems

Stephen Kosonocky
IBM T. J. Watson Research Center

Tuesday, October 23, 2001
4:00 PM (reception 3:30)
Edgerton Hall, Room 34-101
MTL VLSI Seminar

Abstract

As CMOS technology scales to deep submicron lengths, designers face new challenges in determining the proper balance of aggressive high performancen devices and lower performance devices to optimize system power and performance for a given application. Determining this balance is crucial for battery powered handheld devices where device leakage and active power limit the available system performance. This talk will explore this question and describe research in developing low power communication systems which exploit the capabilities of advanced CMOS technology.