MIT Electrical Engineering and Computer Science Fall 2000 Catalogue Supplement

6.979 High Performance Digital Architecture and Implementation (H)

MW 4-5:30, Room 34-302
Dr. Thomas Knight, Room NE43-818, 3-7807
Prereq.: 6.004
3-0-9

Qualifies as a subject in the Computer Systems Architecture Engineering Concentration

Architecture, circuit, and packaging technology for high performance digital systems. Basics of inverter and gate design, digital signaling, clocking. Detailed analysis of circuit parasitics both on-chip and off-chip; transmission lines. Power-aware design techniques and heat dissipation issues. Arithmetic implementations, floating point, divide. Cache and register file design. Superscalar and out-of-order execution techiques. Interprocessor interconnection networks and large scale parallel machines. Reconfigurable logic. Architectural support for higher level symbolic languages such as Lisp and APL.

Wire parasitics. Estimation of wire resistance, capacitance, inductance Estimation of time constants. RC dominated lines and the diffusion equation. On chip parasitics. Optimal buffering.

LC dominated lines and the wave equation. Transmission lines. Termination. Cable and on PC board parasitics.

Inverter design. Fundmantal equation of digital design. Speed of inverters. Signal restoration. Single and dual rail design. Current flow in inverters. Power supply noise.

Design of simple logic gates. CMOS gate forms. Pass gates. Combinational logic design. Reconfigurable logic.

Power dissipation in digital logic circuits. Power control and reduction techniques. Power recovery techniques.

Combinational arithmetic units. Fast adders and subtractors. Booth multipliers. Flow through divide and square root.

Clocking methodologies. Clock skew. Latch design. Dynamic logic techniques.

Board and system level packaging parasitics. Board level design. Bypassing, power distribution. Heat dissipation.

Sequential logic design. Iterative arithmetic units. SRT divide. Asynchronous clocking issues.

Static RAM design. Static and clocked sense amps and comparators. Associative techniques.

Register file design. Multiport register files. Duplication of register files. Pipeline bypasses.

Uniprocessor cache design. Associative techniques. Write back buffers. Instruction caches. Instruction decode. Decode into the Icache.

Simple RISC processor designs. Superscalar design. Register renaming. Retirement.

Main memory technology. DRAM design. ECC. Bus design. Vector processors.

Multiprocessor memory issues. Multiprocessor interconnection networks. Latency and bandwidth. Responsibility, retry, and error handling. Garbage collection.

Language design issues. Function calling. Side effects. Closures. Generic function (message) handling. Tagged data representation. Data ownership.