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MIT Electrical Engineering and Computer Science
EECS Event |
Tuesday, September 19, 2000
4:00 PM (reception 3:30)
Edgerton Hall, Room 34-101
MTL VLSI Seminar
Abstract
The IA-64™ architecture contains many features that support high performance computing. Control and data speculation, predication, data and instruction prefetch, and support for software pipelining are the most obvious examples. However, it is through the combination of these features that the architecture is able to keep the processor busy.
This talk will introduce these architectural features and give examples of how they combine to increase instruction-level parallelism. The talk will also introduce the micro-architecture of the Itanium™ processor, the first instance of the IA-64 architecture.