|
|
MIT Electrical Engineering and Computer Science
EECS Event |
Tuesday, April 24, 2001
4:00 PM (reception 3:30)
Edgerton Hall, Room 34-101
MTL VLSI Seminar
Abstract
The performance of silicon CMOSFET technology continues to improve by over 20% per year. At IBM, additional performance has been demonstrated with the introduction of silicon-on-insulator technology and copper/low-k dielectric interconnect systems. This presentation will give an overview of the development of the 0.18 and 0.13 micron technologies at IBM and discuss the current research and development activities which will be critical to the continued performance improvement of CMOS technologies in the 0.10 and 0.07 micron technology nodes. The major challenges in the quest to continue on the current performance scaling will be discussed.