MIT Electrical Engineering and Computer Science EECS Event

Device Scaling and Technology Challenges for High-Performance Sub-20nm Gate Length Transistors for the 45nm Logic Generation Node

Robert Chau
Intel Corporation

Tuesday, April 10, 2001
4:00 PM (reception 3:30)
Edgerton Hall, Room 34-101
MTL VLSI Seminar

Abstract

Transistors with sub-20nm physical gate length will be required for the 45nm technology node for logic applications. The device scaling and technology challenges for these ultra-small transistors will be addressed. Research opportunities for universities will also be discussed.