MIT Electrical Engineering and Computer Science EECS Event

The Design and Analysis of the Clock Distribution Network for a 1.2 GHz Alpha Microprocessor

Thucydides (Duke) Xanthopoulos
Compaq Computer Corporation

Tuesday, May 15, 2001
4:00 PM (reception 3:30)
Edgerton Hall, Room 34-101
MTL VLSI Seminar

Abstract

Single-wire, synchronous clocking systems for increasingly large and complex microprocessors present major technical challenges: Die size increases whereas target clock skew and jitter typically remain a constant percentage of a decreasing cycle time. The clocking methodology of the present Alpha microprocessor handles such challenges by radically departing from a single chip-wide clock distribution, in order to better control clock skew, jitter and power dissipation. Four major clocks (one reference and three derived) are used to clock separate chip sections. Delay-locked loops (DLLs) are used to maintain small phase alignment errors among major clocks.

Early studies indicated that transmission line effects have to be taken into account during clock analysis. Low resistance copper interconnects in the absence of reference planes in addition to fast edge rates resulted in inductive wire impedance comparable to pure resistive impedance. Failure to model wire inductance results in clock skew underestimation, signal rise time overestimation and inability to capture signal integrity issues such as overshoots, undershoots and plateaus.